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1 Mbit SPI Serial Flash
A Microchip Technology Company
SST25VF010A
Data Sheet
Write-Enable (WREN)
The Write-Enable (WREN) instruction sets the Write-Enable-Latch bit to 1 allowing Write operations to
occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. CE#
must be driven high before the WREN instruction is executed.
CE#
MODE 3
0 1 2 3 4 5 6 7
SCK
SI
SO
MODE 0
06
MSB
HIGH IMPEDANCE
1265 F12.0
Figure 12: Write Enable (WREN) Sequence
Write-Disable (WRDI)
The Write-Disable (WRDI) instruction resets the Write-Enable-Latch bit and AAI bit to 0 disabling any
new Write operations from occurring. CE# must be driven high before the WRDI instruction is exe-
cuted.
CE#
MODE 3
0 1 2 3 4 5 6 7
SCK
SI
SO
MODE 0
04
MSB
HIGH IMPEDANCE
1265 F13.0
Figure 13: Write Disable (WRDI) Sequence
Enable-Write-Status-Register (EWSR)
The Enable-Write-Status-Register (EWSR) instruction arms the Write-Status-Register (WRSR)
instruction and opens the status register for alteration. The Enable-Write-Status-Register instruction
does not have any effect and will be wasted, if it is not followed immediately by the Write-Status-Regis-
ter (WRSR) instruction. CE# must be driven low before the EWSR instruction is entered and must be
driven high before the EWSR instruction is executed.
?2011 Silicon Storage Technology, Inc.
16
S725081A
10/11
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